This invention relates to backplanes for high speed data processing systems and, in particular, to a backplane wherein the LC product of each trace is minimized
It has long been recognized that the most economical and flexible construction for data processing systems is a backplane having a plurality of connectors for receiving a plurality of printed circuit boards. Each printed circuit board has electrical connections brought out to at least one edge of the board for insertion into a connector. With this construction, the configuration of a data processing system can be changed easily by adding or removing boards.
As used herein, "data processing system" refers to a group of printed circuit boards on a common backplane, wherein at least one of the boards includes digital logic circuitry. The boards can be, but need not be, identical and can include zero, one, or more microprocessors. In the art, the backplane is often referred to as a "motherboard," probably as a derivative of "breadboard." The printed circuit boards attached to the backplane are often referred to as "daughter boards" or "cards." Because of the shape of the connectors, the term "slot" is used in the art to refer to the connector itself or to refer to the position of a connector on a backplane, e.g. "slot six." There is not actually a long, narrow hole in the backplane. A plurality of traces carrying the same type of signals is known as a bus, e.g. a data bus.
The backplane itself is a printed circuit board in which the connectors are approximately parallel and, in general, each pin of each connector is electrically connected to the corresponding pin of every other connector by a conductive run or "trace" among the connectors. For example, pin one in the first connector is connected to pin one of every other connector by a trace threading its way down the length of the backplane. In the early days of the microprocessor, a single layer of traces interconnecting ten or twenty connectors was sufficient. As microprocessors became faster, this construction was no longer adequate and multi-layer sandwiches of traces became necessary.
Each microprocessor has an internal clock that synchronizes the operation of the various portions of the microprocessor, e.g. internal logic, address lines, and data lines, and defines the minimum period in which operations can take place. While not a true indicator of the speed of a microprocessor, the clock frequency provides a simple way to compare microprocessors. A greater difficulty with clock frequency is that the signals in a microprocessor are square wave pulses, not sinusoidal signals. As shown by the mathematician Fourier, a square wave of a given frequency is the sum of a sine wave of the same frequency (the fundamental) and the odd harmonics of the fundamental. Thus, the pulses in a backplane contain components of significantly higher frequency than the nominal clock frequency. The result is that the traces become transmission lines having complex, frequency dependent, impedance characteristics.
If the clock frequency is low, e.g. one megahertz, the parallel lines in a backplane exhibit some coupling, known as cross-talk, i.e. the traces act like miniature antennas, transmitting and receiving signals. This coupling is minimal and the system functions despite the distortions that the coupling introduces into the signals on the traces. Even though the traces are actually transmission lines, the traces can be considered lumped capacitances and inductances at low frequency. If, on the other hand, the clock frequency is on the order of tens of megahertz, the problems of coupling can no longer be ignored and the prior art has used a number of techniques for addressing the problem, e.g. grounding alternate traces to minimize coupling. At a clock frequency on the order of one hundred megahertz, the problems are severe and the traces must be considered transmission lines, with the attendant problems of reflections and terminations.
A square wave pulse is usually considered to have vertical edges and a constant amplitude top. In fact, this ideal is physically impossible to attain, although one can appear to approach the ideal, depending upon how closely one inspects the waveform. For example, a conductive trace of any length exhibits a nominal capacitance. The time required to charge that capacitance to a given voltage depends upon the available current. Increasing a trace from zero volts to five volts (or any voltage) in zero time requires infinite current. Thus, the leading edge and the trailing edge of any square wave pulse necessarily have a finite slope (.DELTA.V/.DELTA.t) and this slope limits the maximum speed of operation of a data processing system and is independent of the clock frequency. On the other hand, it is advantageous to reduce the slopes of the leading and trailing edges of a pulse to reduce the amplitude of the high frequency components of the pulse because even very short traces can radiate significant amounts of energy at very high frequencies. Reducing the slope of the leading edge and the slope of the trailing edge reduces the amount of electromagnetic interference (EMI) caused by a backplane.
A simple rule of thumb is that a trace can be considered a lumped impedance if both the rise time (.DELTA.t.sub.r) and the fall time (.DELTA.t.sub.f) of a pulse are longer than the round trip propagation time of the pulse. If not, the trace must be considered a complex transmission line, i.e. the capacitances and inductances are distributed along the trace and must be evaluated at a plurality of points to determine the effect of the trace on a pulse traveling along the trace (and being reflected back).
At high clock frequencies, the traces on a backplane cause a delay that can become a significant fraction of a clock period. For example, a trace forty centimeters long can delay a pulse by eight to ten nanoseconds or one period of a 100 megahertz clock. The difference in the arrival times of a signal at different connectors is called skew. If all connectors are being driven by a common clock, skew can severely limit the rate at which data is transmitted between boards connected to the backplane. It is known in the art to arrange the boards in a circle to minimize path length but this configuration is difficult to construct. It is preferred to have a planar or "linear" backplane.
It is now known in the art how to address many of the foregoing difficulties. U.S. Pat. No. 5,696,667 (Berding) discloses a technique for converting the impedances of the traces into lumped impedances, with an attendant eight-fold improvement in speed over the prior art where a ten or twenty percent increase would have been welcomed. Despite this tremendous advance in the art, there are applications for which even greater speed is desirable.
The Berding patent describes a backplane in which a set of common points is electrically coupled to the connectors by individual conductive traces between each common point and the corresponding pins of the connectors. A "point" does not refer to a location of zero size but to a finite region in a conductive layer of a printed circuit board.
Compared to backplanes of the prior art, the newer construction increases the number of traces in a backplane because a single trace threading its way among the pins is replaced with a separate trace for each connector. A VME (Versa Module European) backplane typically includes twenty-one connectors. Constructed in accordance with the Berding patent, slot eleven contains the common points and there are ten connectors on either side. Thus, for each pin, there are ten traces extending from slot eleven to slot ten and from slot eleven to slot twelve. The number of traces decreases as one moves to either end of the backplane.
In the manufacture of printed circuit boards, there are a minimum line width and a minimum line spacing that limits the number of traces that can pass between a pair of pins in a connector. To satisfy the limits, one must increase the number of layers. It is difficult to produce large quantities of backplanes at high speed when the backplane contains a large number of layers. The layers of the board must be carefully aligned to assure that contact holes are drilled in the proper places. It is desired to reduce the number of traces without losing the benefit of having a lumped impedance.
It is known in the art to make a long trace wider than a short trace to compensate for the greater resistance of the long trace; e.g. U.S. Pat. No. 5,365,406 (Kurashima). U.S. Pat. No. 5,541,369 (Tahara et al.) disclose printed circuit boards in which a conductive trace increases in width with length. What is not recognized in these patents is that a wider trace has a lower inductance than a narrower trace. More specifically, in terms of a backplane constructed in accordance with the Berding patent, it has not been recognized that a wider trace can reduce the lumped inductance of a trace.
Reducing the lumped impedance of a trace reduces the amount a signal is delayed traveling along a trace. The difference in the arrival times of a signal at different connectors is called skew, which is undesirable. In the prior art, the problem of skew is addressed by making the traces of equal length; e.g. U.S. Pat. No. 4,879,433 (Gillett et al.). Unfortunately, it is not feasible to construct a backplane in accordance with the Berding patent and have traces of equal length.
In view of the foregoing, it is therefore an object of the invention to provide a backplane that is designed for high speed and that is designed for ease of manufacture.
Another object of the invention is to reduce the inductances of longer traces by increasing the width of the remote portions, i.e. portions located away from the common points, of the longer traces.
A further object of the invention is to minimize skew in a backplane for high speed data processing systems.
Another object of the invention is to minimize the LC product of the lumped impedance of each trace in a backplane for high speed data processing systems.